XRT91L34IV-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L34IV-F' PDF : 38 Pages View PDF
XRT91L34
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
The receive serial inputs can also be AC coupled to an optical module or an electrical interface. A simplified
Differential LVPECL AC coupling using external passive components block diagram is shown in Figure 5.
FIGURE 5. RECEIVE SERIAL INPUT INTERFACE USING DIFF LVPECL AC COUPLING INTERNAL TERMINATION
Internal 100 Ohm line-to-line
termination active on
RXDI[3:0]P and RXDI[3:0]N pins
DIFF LVPECL A/C Coupling using
External Passive Components
VBB1.2 100
RXDI0P
RXDI0N
XRT91L34
VBB1.2 100
STS-12/3/1
or
STM-4/1/0
Clock and Data
Recovery
VBB1.2 100
VBB1.2 100
RXDI1P
RXDI1N
RXDI2P
RXDI2N
RXDI3P
RXDI3N
130 x 8
Channel 0
Optical Module
Optical Fiber
Channel 1
Optical Module
Optical Fiber
Channel 2
Optical Module
Optical Fiber
Channel 3
Optical Module
Optical Fiber
Install DC current path resistors
as close to Optical Module
LVPECL output driver pins
NOTE: Some optical modules integrate AC coupling capacitors and DC current path resistors internally within the module.
2.2 Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential receiver
and generates a clock that is the same frequency as the incoming data. The clock recovery block utilizes the
reference clock from REFCLKP/N or TTLREFCLK to train and monitor its clock recovery PLL. Upon startup,
the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock onto the
incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local
reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch to the
local reference clock, declare a Loss of Lock and output a high level signal on the LOL output pin. Whenever a
Loss of Lock (LOL) or a Loss of Signal (LOS) event occurs, the CDR will continue to supply a receive clock
(based on the local reference). When the SDEXT becomes active and internal DLOS is cleared and the
recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference source, the
clock recovery PLL will switch back to the incoming receive serial data stream. Table 3 specifies the Clock and
Data Recovery Unit performance characteristics.
15
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