XRT91L34IV-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L34IV-F' PDF : 38 Pages View PDF
XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
REV. 1.0.1
4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK
The Serial Microprocessor Interface uses a standard 3-pin serial port with CS, SCLK, and SDI for programming
the device. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the registers,
monitor the device via an interrupt pin, and reset the device to its default configuration by pulling reset "Low"
for more than 10ns. A simplified block diagram of the Serial Microprocessor Interface is shown in Figure 17.
FIGURE 17. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE
SDI
SCLK
Shift Register
Data out
SDO
CS
Status bits and error
Flags from CDRs
Address
bus
Data
bus
Register
Bank
INT
Controls to
CDRs
RESET
4.1 SERIAL TIMING INFORMATION
The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor
Interface samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device
until all 16 bits of serial data have been sampled. A timing diagram of the Serial Microprocessor Interface is
shown in Figure 18.
FIGURE 18. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE
CS
SCLK
SDI
SDO
25nS
50nS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
R/W A0 A1 A2 A3 A4 A5 X D0 D1 D2 D3 D4 D5 D6 D7
High-Z
D0 D1 D2 D3 D4 D5 D6 D7
High-Z
NOTE: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active
"Low") must be de-asserted at the end of each write or read operation.
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