XRT91L34IV-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L34IV-F' PDF : 38 Pages View PDF
XRT91L34
REV. 1.0.1
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
COMMON CONTROL REGISTERS
TABLE 9: MICROPROCESSOR INTERFACE REGISTER 0X00 BIT DESCRIPTION
GLOBAL CONTROL REGISTER (0X00)
BIT
NAME
FUNCTION
Regis- Default
ter
Value
Type (HW Reset)
D7
Reserved This Register Bit is Not Used
RO
0
D6
Reserved This Register Bit is Not Used
RO
0
D5
Reserved This Register Bit is Not Used
RO
0
D4
DLOSDIS DLOS (Digital Loss of Signal) Disable
R/W
0
This global bit is used to disable the channelized internal DLOS
monitoring and automatic muting of RXDO[3:0]P/N recovered data
output pins upon DLOS detection.
"0" = Monitor & Mute recovered data upon LOS declaration
"1" = Disable internal DLOS monitoring
D3
Reserved This Register Bit is Not Used
RO
0
D2
MINT_EN Master Interrupt Enable
"0" = Disables Interrupt generation
"1" = Enables Interrupt generation
R/W
0
D1
CDRREFSEL Clock and Data Recovery Unit Reference Frequency Select
R/W
0
This bit is used to select the clock input reference.
"0" = 77.76 MHz reference frequency support
"1" = 19.44 MHz reference frequency support
D0
SWRST Software Reset
R/W
0
A "0" to "1" transition will asynchronously reset the device and all
register bit settings to their default state. This bit will automatically
reset itself to "0". User does not have to write "0" to this bit to resume
normal operation.
"0" = Normal Operation
"1" = Resets all registers to default values
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