XRT91L34IV-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L34IV-F' PDF : 38 Pages View PDF
XRT91L34
QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR
CHANNELIZED REGISTERS
REV. 1.0.1
TABLE 15: MICROPROCESSOR INTERFACE REGISTER 0X08, 0X10, 0X18, 0X20 BIT DESCRIPTION
CHANNEL CONTROL REGISTER (CH0 = 0X08, CH1 = 0X10, CH2 = 0X18, CH3 = 0X20)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
RO
0
D6
Reserved This Register Bit is Not Used
RO
0
D5
Reserved This Register Bit is Not Used
RO
0
D4
Reserved This Register Bit is Not Used
RO
0
D3
Reserved This Register Bit is Not Used
RO
0
D2
RCLKDISn Recovered Serial Clock Output Disable
R/W
0
This bit is used to control the activity of the 622.08/155.52/51.84
MHz differential serial clock output. Tristating RXCLKOnP/N output
reduces power consumption.
"0" = RXCLKOnP/N output Enabled
"1" = RXCLKOnP/N output Tristated
D1
CDRDISn Clock and Data Recovery Unit Disable
Disables Internal Clock and Data Recovery Unit.
"0" = Internal CDR Unit is Enabled
"1" = Internal CDR Unit is Disabled
R/W
0
D0
POLn
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"0" = SDEXT is active "Low"
"1" = SDEXT is active "High"
R/W
0
NOTE: n denotes channel number.
30
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