XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.1.0
2.0 RECEIVE SECTION
The receive section of XRT91L80 includes the differential inputs RXIP/N, followed by the clock and data
recovery unit (CDR) and receive serial-to-parallel converter (SIPO). The receiver accepts the high speed Non-
Return to Zero (NRZ) serial data at 2.488/2.666 Gbps through the differential input interfaces RXIP/N. The
clock and data recovery unit recovers the high-speed receive clock from the incoming scrambled NRZ data
stream. The recovered serial data is converted into 4-bit-wide 622.08/666.51 Mbps parallel data and presented
to the RXD[3:0]P/N LVDS parallel interface. A divide-by-4 version of the high-speed recovered clock,
RXPCLKOP/N, is used to synchronize the transfer of the 4-bit RXDO[3:0]P/N data with the receive portion of
the upstream device. Upon initialization or loss of signal or loss of lock the 77.76/155.52 MHz (83.31/166.63
MHz) external local reference clock is used to start-up the clock recovery phase-locked loop for proper
operation. A special loop-back feature can be configured when parallel remote loopback (RLOOPP) is used in
conjunction with de-jittered loop-time mode that allows the re-transmitted data to comply with ITU and Bellcore
jitter generation specifications.
2.1 Receive Serial Input
The receive serial CML inputs are applied to RXIP/N. The receive serial inputs can be AC or DC coupled to an
optical module or an electrical interface. A simplified AC coupled block diagram is shown in Figure 4.
FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK
RXIP
RXIN
XRT91L80
STS-48/
STM-16
Transceiver
0.1µF
0.1µF
Optical Module
Optical Fiber
NOTE: Some optical modules integrate AC coupled capacitors within the module. If so, the external AC coupled capacitors
are not necessary and can be excluded.
The 2.488/2.666 Gbps high-speed differential CML RXIP/N input swing characteristics is shown in Table 2.
TABLE 2: DIFFERENTIAL CML INPUT SWING PARAMETERS
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNITS
∆VINDIFF
Differential Input Voltage Swing
200
∆VINSE
Single-Ended Input Voltage Swing
100
∆VINBIAS
Input Bias Range (AC Coupled)
1.0
RDIFF
Differential Input Resistance
75
1000
mV
600
mV
1.4
V
125
Ω
14
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