XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.1.0
TABLE 4: LOSD DECLARATION POLARITY SETTING
SDEXT POLARITY LOSDMUTE INTERNAL SIGNAL DETECT
LOSDET
OUTPUT
CDR PLL
RXDO[3:0]P/N REFERENCE LOCK
0
0
1
Active Low. Optical signal presence
indicated by SDEXT logic 0 input
Low
from optical module.
Normal
Operation
Hi-Spd Received
Data
0
1
1
0
1
Active High. Optical signal presence
indicated by SDEXT logic 1 input
from optical module.
High
LOSD
declared
Muted
Local Reference
Clock
1
Active Low. Optical signal presence
High
indicated by SDEXT logic 0 input
from optical module.
LOSD
declared
Muted
Local Reference
Clock
1
1
1
Active High. Optical signal presence
indicated by SDEXT logic 1 input
Low
from optical module.
Normal
Operation
Hi-Spd Received
Data
2.4 Receive Serial Input to Parallel Output (SIPO)
The SIPO is used to convert the 2.488/2.666 Gbps serial data input to 622.08/666.51 Mbps parallel data output
which can interface to a SONET Framer/ASIC. The SIPO bit de-interleaves the serial data input into a 4-bit
parallel output to RXDO[3:0]P/N. A simplified block diagram is shown in Figure 5.
FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF SIPO
4-bit Parallel LVDS Data Output
RXDO0P/N
b03 b02 b01 b00
RXDO1P/N
b13 b12 b11 b10
RXDO2P/N
b23 b22 b21 b20
time (0)
2.488/2.666 Gbps
b33 b23 b13 b03 b32 b22 b12 b02 b31 b21 b11 b01 b30 b20 b10 b00 RXIP/N
RXDO3P/N
b33 b32 b31 b30
RXPCLKOP/N
622.08/666.51 MHz
2.5 Receive Parallel Output Interface
The 4-bit LVDS 622.08/666.51 Mbps parallel data output of the receive path is used to interface to a SONET
Framer/ASIC synchronized to the recovered clock. A simplified block diagram is shown in Figure 6.
FIGURE 6. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK
SONET Framer/ASIC
RXDO0P/N
RXDO1P/N
RXDO2P/N
RXDO3P/N
RXPCLKOP/N
RXCLKO16P/N
XRT91L80
STS-48/STM-16
Transceiver
SDEXT
POLARITY
LOSDMUTE
DISRD
16
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