XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
xr
REV. P1.1.0
PRELIMINARY
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
2.6 Receive Parallel Interface LVDS Operation
When operating the 4-bit Differential bus in LVDS mode, a 402Ω external resistor is needed across XRES1P
and XRES1N to properly bias the RXDO[3:0]P/N and RXPCLKOP/N pins. Figure 7 shows the proper biasing
resistor installed.
FIGURE 7. LVDS EXTERNAL BIASING RESISTORS
402Ω
+/- 1 % tolerance
pin G1 XRES1P
XRES1N pin F1
2.7 Parallel Receive Data Output Mute Upon LOSD
The parallel receiver data outputs can be automatically forced "Low" during an LOSD condition to prevent data
chattering. However, the user must select the proper SDEXT polarity for the optical module used. By asserting
LOSDMUTE "High", the parallel receiver data outputs will be forced "Low" any time an LOSD condition occurs.
2.8 Parallel Receive Data Output Disable
Unlike LOSDMUTE, DISRD is used to asynchronously force the parallel receiver data outputs to zero,
regardless of the data input stream. By asserting DISRD "High", the parallel receiver data outputs will
immediately mute.
2.9 Receive Parallel Data Output Timing
The receive parallel data output from the STS-48/STM-16 receiver will adhere to the setup and hold times
shown in Figure 8 and Table 5.
FIGURE 8. RECEIVE PARALLEL OUTPUT TIMING
RXPCLKOP/N
RXDO[3:0]P/N
tRX_INV
tRX_DEL
tRXPCLKO
tRX_INV
SAMPLE WINDOW
tRX_DEL
TABLE 5: RECEIVE PARALLEL DATA AND CLOCK OUTPUT TIMING SPECIFICATIONS
SYMBOL
tRXPCLKO
tRXPCLKO
tRX_INV
tRX_DEL
RXDUTY
PARAMETER
Receive parallel clock output period (622.08 MHz non-FEC rate)
Receive parallel clock output period (666.51 MHz FEC rate)
RXPCLKOP/N "High" to data invalid window
RXPCLKOP/N "High" to data delay
RXPCLKOP/N Duty Cycle
MIN
TYP
MAX UNITS
1608
ps
1500
ps
200 ps
200 ps
45
55
%
17
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