XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.1.0
3.0 TRANSMIT SECTION
The transmit section of the XRT91L80 accepts 4-bit parallel LVDS data and converts it to serial CML data
output intented to interface to an optical module. It consists of a 4-bit parallel LVDS interface, a 4x9 FIFO,
Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Current Mode Logic (CML) differential line driver,
and Loop Timing modes. The CML serial data output rate is 2.488/2.666 Gbps for STS-48/STM-16
applications. The high frequency serial clock is synthesized by a PLL, which uses a low frequency clock as its
input reference. In order to synchronize the data transfer process, the synthesized 2.488/2.666 GHz serial
clock output is divided by four and the 622.08/666.51 MHz clock is presented to the upstream device to be
used as its timing source.
3.1 Transmit Parallel Input Interface
The parallel data from an upstream device is presented to the XRT91L80 through a 4-bit LVDS parallel bus
interface TXDI[3:0]P/N. The data is latched into a parallel input register on the rising edge of TXPCLKIP/N. If
the SONET Framer/ASIC is synchronized to the same timing source as the XRT91L80, the transmit data and
clock input can directly interface to the STS-48/STM-16 transceiver. However, if the SONET Framer/ASIC is
synchronized to a separate crystal, the XRT91L80 has two clock output references that can be used to
synchronize the SONET Framer/ASIC. TXPCLKOP/N is a 622.08/666.51 MHz LVDS clock output source that
is derived from the CMU synthesized high-speed clock. TXCLKO16P/N is a 155.52/166.63 MHz LVDS
auxiliary clock output source that is also derived from the CMU synthesized high-speed clock. Either of these
two clock output sources can be used to synchronize the SONET Framer/ASIC to the XRT91L80. If the
auxiliary clock source is not used, it can be disabled by pulling TXCLKO16DIS "High". A simplified block
diagram of the parallel interface is shown in Figure 9.
FIGURE 9. TRANSMIT PARALLEL INPUT INTERFACE BLOCK
SONET Framer/ASIC
TXDI0P/N
TXDI1P/N
TXDI2P/N
TXDI3P/N
TXPCLKIP/N
TXPCLKOP/N
XRT91L80
STS-48/STM-16
Transceiver
TXCLKO16P/N
TXCLKO16DISP/N
18
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