5962-9750701HXC View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'5962-9750701HXC' PDF : 44 Pages View PDF
Asynchronous Read/Write—Host to AD14060/AD14060L
Use these specifications for asynchronous host processor accesses
of an AD14060/AD14060L, after the host has asserted CS and
HBR (low). After HBG is returned by the AD14060/
AD14060/AD14060L
AD14060L, the host can drive the RD and WR pins to access
the AD14060/AD14060L’s internal memory or IOP registers.
HBR and HBG are assumed low for this timing.
Parameter
Read Cycle
Timing Requirements:
tSADRDL
tHADRDH
tWRWH
tDRDHRDY
tDRDHRDY
Address Setup/CS Low Before RD Low1
Address Hold/CS Hold Low After RD
RD/WR High Width
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
5V
Min
Max
0.5
0.5
6
0.5
0.5
3.3 V
Min
Max
0.5
0.5
6
0.5
0.5
Units
ns
ns
ns
ns
ns
Switching Characteristics:
tSDATRDY
tDRDYRDL
tRDYPRD
tHDARWH
Data Valid Before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After RD High
1.5
11
45 + DT
1.5
9
1.5
ns
11.5
ns
45 + DT
ns
1.5
9.5
ns
Write Cycle
Timing Requirements:
tSCSWRL
CS Low Setup Before WR Low
0.5
0.5
ns
tHCSWRH
CS Low Hold After WR High
0.5
0.5
ns
tSADWRH
Address Setup Before WR High
5.5
5.5
ns
tHADWRH
Address Hold After WR High
2.5
2.5
ns
tWWRL
WR Low Width
7
7
ns
tWRWH
RD/WR High Width
6
6
ns
tDWRHRDY WR High Delay After REDY (O/D) or (A/D) Disable
0.5
0.5
ns
tSDATWH
Data Setup Before WR High
5.5
5.5
ns
tHDATWH
Data Hold After WR High
1.5
1.5
ns
Switching Characteristics:
tDRDYWRL REDY (O/D) or (A/D) Low Delay After WR/CS Low
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
11
11.5
ns
15
15
ns
1 + 7DT/16 9 + 7DT/16 0 + 7DT/16 8 + 7DT/16 ns
NOTE
1Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31–0 must be a non-MMS value 1/2 tCLK before RD
or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be
driven during asynchronous host accesses, see Table 8.2 of the ADSP-2106x SHARC User’s Manual.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 19a. Synchronous REDY Timing
REV. A
–25–
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