5962-9750701HXC View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'5962-9750701HXC' PDF : 44 Pages View PDF
AD14060/AD14060L
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0,
ACK, and DMAG signals. For Paced Master mode, the data
transfer is controlled by ADDR31-0, RD, WR, MS3-0, and ACK
(not DMAG). For Paced Master mode, the “Memory Read–Bus
Master”, “Memory Write–Bus Master”, and “Synchronous
Read/Write–Bus Master” timing specifications for ADDR31-0,
RD, WR, MS3-0, SW, PAGE, DATA47-0, and ACK also apply.
Parameter
Timing Requirements:
tSDRLC
tSDRHC
tWDR
tSDATDGL
tHDATIDG
tDATDRH
tDMARLL
tDMARH
DMARx Low Setup Before CLKIN1
DMARx High Setup Before CLKIN1
DMARx Width Low (Nonsynchronous)
Data Setup After DMAGx Low2
Data Hold After DMAGx High
Data Valid After DMAGx High2
DMAGx Low Edge to Low Edge
DMAGx Width High
5V
Min
5
5
6
2.5
23 + 7DT/8
6
3.3 V
Max
Min
Max
Units
9.5 + 5DT/8
15.5 + 7DT/8
5
5
6
2.5
23 + 7DT/8
6
ns
ns
ns
9.5 + 5DT/8 ns
ns
15.5 + 7DT/8 ns
ns
ns
Switching Characteristics:
tDDGL
tWDGH
DMAGx Low Delay After CLKIN
DMAGx High Width
tWDGL
tHDGC
tVDATDGH
DMAGx Low Width
DMAGx High Delay After CLKIN
Data Valid Before DMAGx High3
tDATRDGH
tDGWRL
tDGWRH
Data Disable After DMAGx High4
WR Low Before DMAGx Low
DMAGx Low Before WR High
tDGWRR
tDGRDL
tDRDGH
WR High Before DMAGx High
RD Low Before DMAGx Low
RD Low Before DMAGx High
tDGRDR
tDGWR
tDADGH
RD High Before DMAGx High
DMAGx High to WR, RD, DMAGx Low
Address/Select Valid to DMAGx High
tDDGHA
Address/Select Hold after DMAGx High
9 + DT/4
16 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
7 – DT/8
7.5 + 9DT/16
–0.5
8
–0.5
2.5
9.5 + 5DT/8 + W
0.5 + DT/16
3.5 + DT/16
–0.5
2
10.5 + 9DT/16 + W
–0.5
3.5
4.5 + 3DT/8 + HI
16 + DT
–1
9 + DT/4
16 + DT/4
ns
6 + 3DT/8
ns
12 + 5DT/8
ns
–2 – DT/8
7 – DT/8
ns
7.5 + 9DT/16
ns
–0.5
8
ns
–0.5
2.5
ns
9.5 + 5DT/8 + W
ns
0.5 + DT/16
3.5 + DT/16 ns
–0.5
2
ns
10.5 + 9DT/16 + W
ns
–0.5
3.5
ns
4.5 + 3DT/8 + HI
ns
16 + DT
ns
–1
ns
W = (number of wait states specified in WAIT register) Ă— tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1Only required for recognition in the current cycle.
2tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven tDATDRH after DMARx is brought high.
3tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 7.5 + 9DT/16 + (n Ă— tCK)
where n equals the number of extra cycles that the access is prolonged.
4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
–28–
REV. A
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