5962-9750701HXC View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'5962-9750701HXC' PDF : 44 Pages View PDF
AD14060/AD14060L
Three-State TimingโBus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
Parameter
Timing Requirements:
tSTSCK
tHTSCK
SBTS Setup Before CLKIN
SBTS Hold Before CLKIN
5V
Min
Max
3.3 V
Min
12 + DT/2
12 + DT/2
5.5 + DT/2
Switching Characteristics:
tMIENA
tMIENS
tMIENHG
tMITRA
tMITRS
tMITRHG
tDATEN
tDATTR
tACKEN
tACKTR
tADCEN
tADCTR
tMTRHBG
tMENHBG
Address/Select Enable After CLKIN
Strobes Enable After CLKIN1
HBG Enable After CLKIN
Address/Select Disable After CLKIN
Strobes Disable After CLKIN1
HBG Disable After CLKIN
Data Enable After CLKIN2
Data Disable After CLKIN2
ACK Enable After CLKIN2
ACK Disable After CLKIN2
ADRCLK Enable After CLKIN
ADRCLK Disable After CLKIN
Memory Interface Disable Before HBG Low3
Memory Interface Enable After HBG High3
โ1.5 โ DT/8
โ1.5 โ DT/8
โ1.5 โ DT/8
9 + 5DT/16
0 โ DT/8
7.5 + DT/4
โ1 โ DT/8
โ2 โ DT/8
โ1 + DT/8
18.5 + DT
1 โ DT/4
2.5 โ DT/4
3 โ DT/4
8 โ DT/8
7 โ DT/8
9 โ DT/4
โ1.25 โ DT/8
โ1.5 โ DT/8
โ1.5 โ DT/8
9 + 5DT/16
0 โ DT/8
7.5 + DT/4
โ1 โ DT/8
โ2 โ DT/8
โ1 + DT/8
18.5 + DT
NOTES
1Strobes = RD, WR, SW, PAGE, DMAG.
2In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
Max
5.5 + DT/2
1 โ DT/4
2.5 โ DT/4
3 โ DT/4
8 โ DT/8
7 โ DT/8
9 โ DT/4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN
SBTS
MEMORY
INTERFACE
DATA
ACK
ADRCLK
tMIENA, tMIENS, tMIENHG
tDATEN
tACKEN
tADCEN
tSTSCK
tHTSCK
tMITRA, tMITRS, tMITRHG
tDATTR
tACKTR
tADCTR
HBG
MEMORY
INTERFACE
tMENHBG
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 20. Three-State Timing
REV. A
โ27โ
tMTRHBG
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