ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
EPROM Mode
FINAL
DATASHEET
This mode is suitable for use with an EPROM, in which configuration data is stored (one-way communication - status
information will not be accessible). A state machine internal to the ACS8520 device will perform numerous EPROM
read operations to read the data out of the EPROM. In EPROM Mode, the ACS8520 takes control of the bus as Master
and reads the device set-up from an AMD AM27C64 type EPROM at lowest speed (250ns) after device set-up (system
reset). The EPROM access state machine in the up interface sequences the accesses. Figure 21 shows the access
timing of the device in EPROM mode.
Further information can be found in the AMD AM27C64 datasheet.
Figure 21 Access Timing in EPROM mode
CSB (=OEB)
A
AD
Z
address
tacc
data
Z
F8110D_015ReadAccEEPROM_01
Table 29 Access Timing in EPROM mode (For use with Figure 21)
Symbol
tacc
Parameter
Delay CSBfalling edge or A change to AD valid
MIN
TYP
MAX
-
-
920 ns
Power-On Reset
The Power-On Reset (PORB) pin resets the device if forced Low. The reset is asynchronous, the minimum Low pulse
width is 5 ns. Reset is needed to initialize all of the register values to their defaults. Reset must be asserted at power
on, and may be re-asserted at any time to restore defaults. This is implemented simply using an external capacitor to
GND along with the internal pull-up resistor. The ACS8520 is held in a reset state for 250 ms after the PORB pin has
been pulled High. In normal operation PORB should be held High.
Revision 3.02/October 2005 © Semtech Corp.
Page 52
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