ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Table 30 Register Map (cont...)
FINAL
DATASHEET
Register Name
Data Bit
RO = Read Only
R/W = Read/Write
7 (MSB)
6
5
4
3
2
1
0 (LSB)
cnfg_output_frequency (R/W)
(TO1 & TO2) 60 85
output_freq_2 (TO2)
output_freq_1 (TO1)
(TO3 & TO4) 61 86
output_freq_4 (TO4)
output_freq_3 (TO3)
(TO5 & TO6) 62 8A
output_freq_6 (TO6)
output_freq_5 (TO5)
(TO7 to TO11) 63 F6 MFrSync
enable
FrSync enable TO9 enable TO8 enable
output_freq_7 <TO7>
cnfg_T4_DPLL_frequency (R/W) 64 01
Auto Disable AMI Duty cycle T4 SONET/
T4 output
SDH selection
T4_DPLL_frequency
cnfg_T0_DPLL_frequency (R/W)
65 01 T4 for
measuring T0
phase
T4 APLL for T0
E1/DS1
T0 Freq to T4 APLL
T0_DPLL_frequency
cnfg_T4_DPLL_bw (R/W)
66 00
T4_DPLL_bandwidth [1:0]
cnfg_T0_DPLL_locked_bw (R/W) 67 0B
T0_DPLL_locked_bandwidth [4:0]
cnfg_T0_DPLL_acq_bw (R/W) 69 0F
T0_DPLL_acquisition_bandwidth [4:0]
cnfg_T4_DPLL_damping (R/W) 6A 13
T4_PD2_gain_alog_8K [6:4]
T4_damping [2:0]
cnfg_T0_DPLL_damping (R/W) 6B 13
T0_PD2_gain_alog_8K [6:4]
T0_damping [2:0]
cnfg_T4_DPLL_PD2_gain (R/W) 6C C2 T4_PD2_gain_
enable
T4_PD2_gain_alog [6:4]
T4_PD2_gain_digital [2:0]
cnfg_T0_DPLL_PD2_gain (R/W) 6D C2 T0_PD2_gain_
enable
T0_PD2_gain_alog [6:4]
T0_PD2_gain_digital [2:0]
cnfg_phase_offset (R/W) [7:0] 70 00
phase_offset_value[7:0]
[15:8] 71 00
phase_offset_value[15:8]
cnfg_PBO_phase_offset (R/W) 72 00
PBO_phase_offset [5:0]
cnfg_phase_loss_fine_limit (R/W) 73 A2 Fine limit
Phase loss
enable (1)
No activity for Test bit
phase loss
Set to 1
phase_loss_fine_limit [2:0]
cnfg_phase_loss_coarse_limit
(R/W)
74 85 Coarse limit
Phase loss
enable (2)
Wide range
enable
Enable Multi
Phase resp.
Phase loss coarse limit in UI p-p [3:0]
cnfg_phasemon (R/W)
76 06 Input noise
window enable
sts_current_phase (RO) [7:0] 77 00
current_phase[7:0]
[15:8] 78 00
current_phase[15:8]
cnfg_phase_alarm_timeout
(R/W)
79 32
Timeout value in 2s intervals [5:0]
cnfg_sync_pulses (R/W)
7A 00 2 k/8 k out
from T4
8 k invert
8 k pulse
enable
2 k invert
2 k pulse
enable
cnfg_sync_phase (R/W)
7B 00 indep_FrSync/ Sync_OC-N_
MFrSync
rates
Sync_phase
cnfg_sync_monitor (R/W)
7C 2B ph_offset_
ramp
Sync_monitor_limit
Sync_reference_source
cnfg_interrupt (R/W)
7D 02
GPO interrupt Interrupt
enable
tristate
enable
Interrupt
polarity
enable
cnfg_protection(R/W)
7E 85
protection_value
cnfg_uPsel (R/W)
7F 02
*
Microprocessor type (*Default value depends on
value on UPSEL[2:0] pins)
Revision 3.02/October 2005 © Semtech Corp.
Page 56
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