ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 03
Register Name test_register1
FINAL
DATASHEET
Description
(R/W) Register containing various Default Value 0001 0100
test controls (not normally used).
Bit 7
phase_alarm
Bit 6
disable_180
Bit 5
Bit 4
Bit 3
resync_analog Set to zero
Bit 2
Bit 1
8k Edge Polarity Set to zero
Bit 0
Set to zero
Bit No.
Description
Bit Value Value Description
7
phase_alarm (phase alarm (R/O))
Instantaneous result from T0 DPLL
6
disable_180
Normally the DPLL will try to lock to the nearest
edge (±180°) for the first 2 seconds when locking to
a new reference. If the DPLL does not determine
that it is phase locked after this time, then the
capture range reverts to ±360°, which corresponds
to frequency and phase locking. Forcing the DPLL
into frequency locking mode may reduce the time to
frequency lock to a new reference by up to 2
seconds. However, this may cause an unnecessary
phase shift of up to 360° when the new and old
references are very close in frequency and phase.
5
Not used.
4
resync_analog (analog dividers re-synchronization)
The analog output dividers include a
synchronization mechanism to ensure phase lock at
low frequencies between the input and the output.
3
Test Control
Leave unchanged or set to 0
2
8k Edge Polarity
When lock 8k mode is selected for the current input
reference source, this bit allows the system to lock
on either the rising or the falling edge of the input
clock.
1
Test Control
Leave unchanged or set to zero
0
Test Control
Leave unchanged or set to zero
0
T0 DPLL reporting phase locked.
1
T0 DPLL reporting phase lost.
0
T0 DPLL automatically determines frequency lock
enable.
1
T0 DPLL forced to always frequency and phase lock.
-
-
0
Analog divider only synchronized during first 2
seconds after power-up.
1
Analog dividers always synchronized.This keeps the
clocks divided down from the APLL output, in sync
with equivalent frequency digital clocks in the DPLL.
Hence ensuring that 6.48 MHz output clocks, and
above, are in sync with the DPLL even though only a
77.76 MHz clock drives the APLL.
0
-
0
Lock to falling clock edge.
1
Lock to rising clock edge.
0
-
0
-
Revision 3.02/October 2005 © Semtech Corp.
Page 58
www.semtech.com
Share Link: 
