ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Table 30 Register Map (cont...)
FINAL
DATASHEET
Register Name
Data Bit
RO = Read Only
R/W = Read/Write
7 (MSB)
6
5
4
3
2
1
0 (LSB)
cnfg_input_mode
(Bit 1 RO, otherwise R/W)
34 C2 auto_extsync_ phalarm_
en
timeout
XO_ edge
man_holdover extsync_en
ip_sonsdhb
master_slaveb reversion_
mode
cnfg_T4_path (R/W)
35 40 lock_T4_to_T0 T4_dig_
feedback
T4_op_
from_T0
T4_forced_reference_source
cnfg_differential_inputs (R/W) 36 02
I6_PECL
I5_LVDS
cnfg_uPsel_pins (RO)
37 02
Microprocessor type
cnfg_dig_outputs_sonsdh (R/W) 38 1F
dig2_sonsdh dig1_sonsdh
cnfg_digtial_frequencies (R/W) 39 08
digital2_frequency
digital1_frequency
cnfg_differential_outputs (R/W) 3A C6
T07_PECL_LVDS
T06_LVDS_PECL
cnfg_auto_bw_sel (R/W)
3B FB auto_BW_sel
T0_lim_int
cnfg_nominal_frequency [7:0] 3C 99
Nominal frequency [7:0]
(R/W)
[15:8] 3D 99
Nominal frequency [15:8]
cnfg_holdover_frequency [7:0] 3E 00
Holdover frequency [7:0]
(R/W)
[15:8] 3F 00
Holdover frequency [15:8]
cnfg_holdover_modes (R/W)
40 88 auto_
averaging
fast_averaging read_average
mini_holdover_mode
Holdover frequency [18:16]
(with Registers 3E and 3F above)
cnfg_DPLL_freq_limit (R/W) [7:0] 41 76
DPLL frequency offset limit [7:0]
[9:8] 42 00
DPLL frequency offset limit [9:8]
cnfg_interrupt_mask (R/W) [7:0] 43 00 I8 interrupt not I7 interrupt not I6 interrupt not I5 interrupt not I4 interrupt not I3 interrupt not I2 interrupt not I1 interrupt not
masked
masked
masked
masked
masked
masked
masked
masked
[15:8] 44 00 Operating_ Main_ref_
I14 interrupt
mode interrupt failed interrupt not masked
not masked not masked
I13 interrupt
not masked
I12 interrupt
not masked
I11 interrupt
not masked
I10 interrupt
not masked
I9 interrupt not
masked
[23:16] 45 00 Sync_ip_
T4_status
alarm interrupt interrupt not
not masked masked
T4_inputs_ AMI2_Viol
failed interrupt interrupt not
not masked masked
AMI2_LOS
interrupt not
masked
AMI1_Viol
interrupt not
masked
AMI1_LOS
interrupt not
masked
cnfg_freq_divn (R/W)
[7:0] 46 FF
divn_value [7:0]
[13:8] 47 3F
divn_value [13:8]
cnfg_monitors (R/W)
48 05 freq_mon_clk los_flag_
on_ TDO
ultra_fast_
switch
ext_switch
PBO_freeze PBO_en
freq_monitor_ freq_monitor_
soft_enable hard_enable
cnfg_freq_mon_threshold (R/W) 49 23
soft_frequency_alarm_threshold [3:0]
hard_frequency_alarm_threshold [3:0]
cnfg_current_freq_mon_
threshold (R/W)
4A 23
current_soft_frequency_alarm_threshold [3:0]
current_hard_frequency_alarm_threshold [3:0]
cnfg_registers_source_select
(R/W)
4B 00
T4_T0_select
frequency_measurement_channel_select [3:0]
sts_freq_measurement (R/W) 4C 00
freq_measurement_value [7:0]
cnfg_DPLL_soft_limit (R/W)
4D 8E Freq limit
Phase loss
enable
DPLL Frequency Soft Alarm Limit [6:0] Resolution = 0.628 ppm
cnfg_upper_threshold_0 (R/W) 50 06
Configuration 0: Activity alarm set threshold [7:0]
cnfg_lower_threshold_0 (R/W) 51 04
Configuration 0: Activity alarm reset threshold [7:0]
cnfg_bucket_size_0 (R/W)
52 08
Configuration 0: Activity alarm bucket size [7:0]
cnfg_decay_rate_0 (R/W)
53 01
Cfg 0:decay_rate [1:0]
cnfg_upper_threshold_1 (R/W) 54 06
Configuration 1: Activity alarm set threshold [7:0]
cnfg_lower_threshold_1 (R/W) 55 04
Configuration 1: Activity alarm reset threshold [7:0]
cnfg_bucket_size_1 (R/W)
56 08
Configuration 1: Activity alarm bucket size [7:0]
cnfg_decay_rate_1 (R/W)
57 01
Cfg 1:decay_rate [1:0]
cnfg_upper_threshold_2 (R/W) 58 06
Configuration 2: Activity alarm set threshold [7:0]
cnfg_lower_threshold_2 (R/W) 59 04
Configuration 2: Activity alarm reset threshold [7:0]
cnfg_bucket_size_2 (R/W)
5A 08
Configuration 2: Activity alarm bucket size [7:0]
cnfg_decay_rate_2 (R/W)
5B 01
Cfg 2:decay_rate [1:0]
cnfg_upper_threshold_3 (R/W) 5C 06
Configuration 3: Activity alarm set threshold [7:0]
cnfg_lower_threshold_3 (R/W) 5D 04
Configuration 3: Activity alarm reset threshold [7:0]
cnfg_bucket_size_3 (R/W)
5E 08
Configuration 3: Activity alarm bucket size [7:0]
cnfg_decay_rate_3 (R/W)
5F 01
Cfg 3:decay_rate [1:0]
Revision 3.02/October 2005 © Semtech Corp.
Page 55
www.semtech.com
Share Link: 
