ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 6B (cont...)
Register Name cnfg_DPLL1_damping
FINAL
DATASHEET
Description
(R/W) Register to configure the
damping factor of DPLL1, along
with the gain of the Phase
Detector 2 in some modes.
Default Value
0001 0100
Bit 7
Bit 6
Bit 5
Bit 4
DPLL1_PD2_gain_alog_8k
Bit 3
Bit 2
Bit 1
DPLL1_damping
Bit 0
Bit No.
Description
Bit Value Value Description
[2:0]
DPLL1_damping
Register to configure the damping factor of DPLL1.
The bit values correspond to different damping
factors, depending on the bandwidth selected.
The Gain Peak for the Damping Factors given in the
Value Description (right) are the same as those
tabulated in the description for Reg. 6A.
Damping Factor Damping Factor Damping Factor
for Bandwidth for Bandwidth for Bandwidth
of 18 Hz:
of 35 Hz:
of 70 Hz:
001
1.2
1.2
1.2
010
2.5
2.5
2.5
011
5
5
5
100
5
10
10
101
5
10
20
Address (hex): 6C
Register Name cnfg_DPLL2_PD2_gain
Description
(R/W) Register to configure the Default Value
gain of Phase Detector 2 in some
modes for DPLL2.
1100 0010
Bit 7
DPLL2_PD2_
gain_enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DPLL2_PD2_gain_digital
Bit No.
Description
Bit Value Value Description
7
DPLL2_PD2_gain_enable
[6:3]
[2:0]
Not used.
DPLL2_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking in digital feedback mode. This setting
is always used if gain is disabled in Bit 7,
DPLL2_PD2_gain_enable.
0
DPLL2 Phase Detector 2 not used.
1
DPLL2 Phase Detector 2 gain enabled and choice of
gain determined according to the locking mode:
- digital feedback mode
- analog feedback mode
-
-
-
Gain value of Phase Detector 2 when locking in
digital feedback mode.
Revision 4.01/June 2006 © Semtech Corp.
Page 53
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