ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 7A
Register Name cnfg_sync_pulses
FINAL
Description
(R/W) Register to configure the
Sync outputs available from
FrSync and MFrSync and select
the source for the 2 kHz and
8 kHz outputs from O1 and O2.
DATASHEET
Default Value 0000 0000
Bit 7
2k_8k_from_
DPLL2
Bit 6
Bit 5
Bit 4
Bit 3
8k_invert
Bit 2
8k_pulse
Bit 1
2k_invert
Bit 0
2k_pulse
Bit No.
Description
Bit Value Value Description
7
[6:4]
3
2
1
0
2k_8k_from_DPLL2
Register to select the source (DPLL1 or DPLL2) for
the 2 kHz and 8 kHz outputs available from O1 and
O2.
Not used.
8k_invert
Register bit to invert the 8 kHz output from FrSync.
8k_pulse
Register bit to enable the 8 kHz output from FrSync
to be either pulsed or 50:50 duty cycle. Output 02
must be enabled to use “pulsed output” mode on
the FrSync output, and then the pulse width on the
FrSync output will be equal to the period of the
output programmed on O2.
2k_invert
Register bit to invert the 2 kHz output from
MFrSync.
2k_pulse
Register bit to enable the 2 kHz output from
MFrSync to be either pulsed or 50:50 duty cycle.
Output 03 must be enabled to use “pulsed output”
mode on the MFrSync output, and then the pulse
width on the MFrSync output will be equal to the
period of the output programmed on O3.
0
2/8 kHz on O1 and O2 generated from DPLL1.
1
2/8 kHz on O1 and O2 generated from DPLL2.
-
-
0
8 kHz FrSync output not inverted.
1
8 kHz FrSync output inverted.
0
8 kHz FrSync output not pulsed.
1
8 kHz FrSync output pulsed.
0
2 kHz MFrSync output not inverted.
1
2 kHz MFrSync output inverted.
0
2 kHz MFrSync output not pulsed.
1
2 kHz MFrSync output pulsed.
Revision 4.01/June 2006 © Semtech Corp.
Page 58
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