ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 73
Register Name cnfg_phase_loss_fine_limit
FINAL
DATASHEET
Description
(R/W) Register to configure some Default Value
of the parameters of the DPLL
phase detectors.
1010 0010
Bit 7
fine_limit_en
Bit 6
Bit 5
noact_ph_loss narrow_en
Bit 4
Bit 3
Bit 2
Bit 1
phase_loss_fine_limit
Bit 0
Bit No.
Description
Bit Value Value Description
7
6
5
[4:3]
[2:0]
fine_limit_en
Register bit to enable the phase_loss_fine_limit
Bits [2:0]. When disabled, phase lock/loss is
determined by the other means within the device.
This must be disabled when multi-UI jitter tolerance
is required, see Reg. 74,
cnfg_phase_loss_course_limit.
noact_ph_loss
The DPLL detects that an input has failed very
rapidly. Normally, when the DPLL detects this
condition, it does not consider phase lock to be lost
and will phase lock to the nearest edge (±180º)
when a source becomes available again, hence
giving tolerance to missing cycles. If phase loss is
indicated, then frequency and phase locking is
instigated (±360º locking). This bit can be used to
force the DPLL to indicate phase loss immediately
when no activity is detected.
narrow_en (test control bit)
Set to 1 (default value).
Not used.
phase_loss_fine_limit
When enabled by Bit 7, this register coarsely sets
the phase limit at which the device indicates phase
lost or locked. The default value of 2 (010) gives a
window size of around ±(90º to 180º). The phase
position of the inputs to the DPLL has to be within
the window limit for 1 – 2 seconds before the device
indicates phase lock. If it is outside the window for
any time then phase loss is immediately indicated.
For most cases the default value of 2 (010) is
satisfactory. The window size changes in proportion
to the value, so a value of 1 (001) will give a narrow
phase acceptance or lock window of approximately
±(45º to 90º).
0
Phase loss indication only triggered by other means.
1
Phase loss triggered when phase error exceeds the
limit programmed in phase_loss_fine_limit,
Bits [2:0].
0
No activity on reference does not trigger phase lost
indication.
1
No activity triggers phase lost indication.
0
Do not use.
1
Set to 1.
-
-
000
Do not use. Indicates phase loss continuously.
001
Small phase window for phase lock indication.
010
Recommended value.
011
)
100
)
101
) Larger phase window for phase lock indication.
110
)
111
)
Revision 4.01/June 2006 © Semtech Corp.
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