ACS8526 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8526' PDF : 74 Pages View PDF
ACS8526 LC/P LITE
ADVANCED COMMUNICATIONS
Address (hex): 6D
Register Name cnfg_DPLL1_PD2_gain
FINAL
DATASHEET
Description
(R/W) Register to configure the Default Value
gain of Phase Detector 2 in some
modes for DPLL1.
1100 0010
Bit 7
DPLL1_PD2_
gain_enable
Bit 6
Bit 5
DPLL1_PD2_gain_alog
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DPLL1_PD2_gain_digital
Bit No.
Description
Bit Value Value Description
7
DPLL1_PD2_gain_enable
[6:4]
3
[2:0]
DPLL1_PD2_gain_alog
Register to control the gain of Phase Detector 2
when locking to a reference, higher than 8 kHz, in
analog feedback mode. This setting is not used if
automatic gain selection is disabled in Bit 7,
DPLL1_PD2_gain_enable.
Not used.
DPLL1_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking to a reference in digital feedback
mode. Automatic gain selection must be enabled
(Bit 7, DPLL1_PD2_gain_enable), for
DPLL1_PD2_gain_digital to have any effect.
0
DPLL1 Phase Detector 2 not used.
1
DPLL1 Phase Detector 2 gain enabled and choice of
gain determined according to the locking mode:
- digital feedback mode
- analog feedback mode
- analog feedback at 8 kHz
-
Gain value of Phase Detector 2 when locking to a
high frequency reference in analog feedback mode.
-
-
-
Gain value of Phase Detector 2 when locking to any
reference in digital feedback mode.
Revision 4.01/June 2006 © Semtech Corp.
Page 54
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