ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 76 Pages View PDF
ADSP-21467/ADSP-21469
DDR2 SDRAM Write Cycle Timing
Table 30. DDR2 SDRAM Write Cycle Timing, VDD_DDR2 Nominal 1.8 V
200 MHz1
225 MHz1
Parameter
Min
Max
Min
Max
Switching Characteristics
tCK
DDR2_CLKx/DDR2_CLKx Period
4.8
tCH
DDR2_CLKx High Pulse Width
2.35
2.75
tCL
tDQSS2
DDR2_CLKx Low Pulse Width
DDR2_CLKx Rise to DDR2_DQSx Rise Delay
2.35
2.75
–0.4
0.4
tDS
Last DDR2_DATA Valid to DDR2_DQSx Delay
0.6
tDH
DDR2_DQSx to First DDR2_DATA Invalid Delay
0.65
tDSS
DDR2_DQSx Falling Edge to DDR2_CLKx Rising Setup 1.95
Time
4.22
2.05
2.45
2.05
2.45
–0.45
0.45
0.5
0.55
1.65
tDSH
DDR2_DQSx Falling Edge Hold Time From DDR2_CLKx 2.05
1.8
Rising
tDQSH
DDR2_DQS High Pulse Width
2.05
1.65
tDQSL
DDR2_DQS Low Pulse Width
2.0
1.65
tWPRE
Write Preamble
0.8
0.8
tWPST
Write Postamble
0.5
0.5
tAS
DDR2_ADDR and Control Setup Time Relative to 1.85
1.65
DDR2_CLKx Rising
tAH
DDR2_ADDR and Control Hold Time Relative to
1.0
0.9
DDR2_CLKx Rising
1 In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed (see Engineer-to-Engineer Note EE-349).
2 Write command to first DQS delay = WL × tCK + tDQSS.
DDR2_CLKx
DDR2_CLKx
DDR2_ADDR
DDR2_CTL
DDR2_DQSn
DDR2_DQSn
DDR2_DATA/DM
tCK
tCH
tCL
tAS
tAH
tDQSS
tDSH
tWPRE tDS
tDH
tDSS
tDQSL
tDQSH
tWPST
Figure 19. DDR2 SDRAM Controller Output AC Timing
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
ns
Rev. B | Page 34 of 76 | March 2013
Share Link: 
