ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 76 Pages View PDF
ADSP-21467/ADSP-21469
tLCLKTWH tLCLKTWL
LAST BYTE
TRANSMITTED
TRFAIRNSSTMBITYTTEED1
LCLK
tDLDCH
tHLDCH
LDAT7–0
OUT
tSLACH
tHLACH
tDLACLK
LACK (IN)
NOTES
The t and t specifications apply only to the LACK falling edge. If these specifications are met, LCLK would extend
SLACH
HLACH
and the dotted LCLK falling edge would not occur as shown. The position of the dotted falling edge can be calculated using
the tLCLKTWH specification. tLCLKTWH Min should be used for t SLACH and tLCLKTWH Max for tHLACH. The tSLACH and tHLACH requirement
apply to the falling edge of LCLK only for the first byte transmitted.
Figure 24. Link Ports—Transmit (Bit 6 Cleared)
The data in Table 36 and timing information in Figure 25 apply
when the LSYNC_EN bit (bit 6 in the LCTLx register) is set.
Table 36. Link Ports—Transmit (Bit 6 Set)
Parameter
Timing Requirements
tSLACH
LACK Setup Before LCLK High
tHLACH
LACK Hold After LCLK High
Switching Characteristics
tDLDCH
Data Delay After LCLK High
tHLDCH
Data Hold After LCLK High
tLCLKTWL
LCLK Width Low
tLCLKTWH
LCLK Width High
tDLACLK
LCLK Low Delay After LACK High
1 For 1:2.5 ratio. For other ratios this specification is 0.5 × tLCLK – 1.
Min
Max
Unit
8.5
ns
0
ns
1
ns
–1
ns
0.5 × tLCLK – 0.4 0.6 × tLCLK + 0.41 ns
0.4 × tLCLK – 0.41 0.5 × tLCLK + 0.4 ns
0.5 × tLCLK + 4
1.5 × tLCLK + 4
ns
Rev. B | Page 40 of 76 | March 2013
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