ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 76 Pages View PDF
ADSP-21467/ADSP-21469
AMI Write
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 32. Memory Write
Parameter
Min
Max
Unit
Timing Requirements
tDAAK
tDSAK
AMI_ACK Delay from Address, Selects1, 2
AMI_ACK Delay from AMI_WR Low 1, 3
tDDR2_CLK – 9.7 + W
ns
W–6
ns
Switching Characteristics
tDAWH
Address, Selects to AMI_WR Deasserted2
tDDR2_CLK – 3.1+ W
ns
tDAWL
Address, Selects to AMI_WR Low2
tDDR2_CLK – 3
ns
tWW
AMI_WR Pulse Width
W – 1.3
ns
tDDWH
Data Setup Before AMI_WR High
tDDR2_CLK – 3.0+ W
ns
tDWHA
Address Hold After AMI_WR Deasserted
H + 0.15
ns
tDWHD
tDATRWH
tWWR
Data Hold After AMI_WR Deasserted
Data Disable After AMI_WR Deasserted4
AMI_WR High to AMI_WR Low5
H
tDDR2_CLK – 1.37 + H
tDDR2_CLK – 1.5+ H
ns
tDDR2_CLK + 4.9 + H
ns
ns
tDDWR
Data Disable Before AMI_RD Low
2tDDR2_CLK – 6
ns
tWDE
AMI_WR Low to Data Enabled
tDDR2_CLK – 3.5
ns
W = (number of wait states specified in AMICTLx register) × tDDR2_CLK, H = (number of hold cycles specified in AMICTLx register) × tDDR2_CLK
1 AMI_ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low).
2 The falling edge of AMI_MSx is referenced.
3 Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
4 See Test Conditions on Page 62 for calculation of hold times given capacitive and dc loads.
5 For Write to Write: tDDR2_CLK + H, for both same bank and different bank. For Write to Read: (3 × tDDR2_CLK) + H, for the same bank and different banks.
AMI_ADDR
AMI_MSx
AMI_WR
AMI_DATA
AMI_ACK
AMI_RD
tDAWL
tWDE
tDAAK
tDSAK
tDAWH
tWW
tDDWH
Figure 21. AMI Write
tDWHA
tWWR
tDATRWH
tDDWR
tDWHD
Rev. B | Page 37 of 76 | March 2013
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