ADSP-21467/ADSP-21469
Shared Memory Bus Request
Use these specifications for passing bus mastership between
processors (BRx).
Table 33. Shared Memory Bus Request
Parameter
Timing Requirements
tSBRI
BRx, Setup Before CLKIN High
tHBRI
BRx, Hold After CLKIN High
Switching Characteristics
tDBRO
tHBRO
BRx Delay After CLKIN High
BRx Hold After CLKIN High
Min
2 × tPCLK + 4
5
1 – tPCLK
Max
20
Unit
ns
ns
ns
ns
CLKIN
BRX(OUT)
BRX(IN)
tHBRO
tDBRO
tSBRI
tHBRI
Figure 22. Shared Memory Bus Request
Rev. B | Page 38 of 76 | March 2013