ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 76 Pages View PDF
ADSP-21467/ADSP-21469
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path length differ-
ence between LDATA and LCLK. Setup skew is the maximum
delay that can be introduced in LDATA relative to LCLK:
(setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is
the maximum delay that can be introduced in LCLK relative to
LDATA: (hold skew = tLCLKTWL min – tHLDCH – tHLDCL).
Table 34. Link Ports—Receive
Parameter
Min
Max
Timing Requirements
tSLDCL
Data Setup Before LCLK Low
tHLDCL
Data Hold After LCLK Low
tLCLKIW
LCLK Period
tLCLKRWL
LCLK Width Low
tLCLKRWH
LCLK Width High
Switching Characteristics
tDLALC
LACK Low Delay After LCLK Low1
0.5
1.5
tLCLK (6 ns)
2.6
2.6
5
12
1 LACK goes low with tDLALC relative to the fall of LCLK after first byte, but does not go low if the receiver's link buffer is not about to fill.
Unit
ns
ns
ns
ns
ns
ns
LCLK
LDAT7–0
LACK (OUT)
tLCLKRWH
tLCLKIW
tLCLKRWL
tSLDCL
IN
tHLDCL
tDLALC
Figure 23. Link Ports—Receive
The data in Table 35 and timing information in Figure 24 apply
when the LSYNC_EN bit (bit 6 in the LCTLx register) is cleared.
Table 35. Link Ports—Transmit (Bit 6 Cleared)
Parameter
Timing Requirements
tSLACH
tHLACH
LACK Setup Before LCLK Low
LACK Hold After LCLK Low
Switching Characteristics
tDLDCH
Data Delay After LCLK High
tHLDCH
tLCLKTWL
Data Hold After LCLK High
LCLK Width Low
tLCLKTWH
LCLK Width High
tDLACLK
LCLK Low Delay After LACK High
1 For 1:2.5 ratio. For other ratios this specification is 0.5 × tLCLK – 1.
Min
8.5
0
–1
0.5 × tLCLK – 0.4
0.4 × tLCLK – 0.41
4
Max
1
0.6 × tLCLK + 0.41
0.5 × tLCLK + 0.4
tLCLK + 8
Unit
ns
ns
ns
ns
ns
ns
ns
Rev. B | Page 39 of 76 | March 2013
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