ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 76 Pages View PDF
ADSP-21467/ADSP-21469
AMI Read
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 31. Memory Read
Parameter
Min
Max
Unit
Timing Requirements
tDAD
tDRLD
Address, Selects Delay to Data Valid1, 2, 3
AMI_RD Low to Data Valid1
tSDS
Data Setup to AMI_RD High
2.5
tHDRH
Data Hold from AMI_RD High4, 5
0
tDAAK
AMI_ACK Delay from Address, Selects2, 6
tDSAK
AMI_ACK Delay from AMI_RD Low4
Switching Characteristics
W + tDDR2_CLK –5.4
ns
W – 3.2
ns
ns
ns
tDDR2_CLK – 9.5 + W
ns
W – 7.0
ns
tDRHA
Address Selects Hold After AMI_RD High
RH + 0.20
ns
tDARL
Address Selects to AMI_RD Low2
tDDR2_CLK – 3.8
ns
tRW
AMI_RD Pulse Width
W – 1.4
ns
tRWR
AMI_RD High to AMI_RD Low
HI + tDDR2_CLK – 1
ns
W = (number of wait states specified in AMICTLx register) × tDDR2_CLK.
RHC = (number of Read Hold Cycles specified in AMICTLx register) × tDDR2_CLK
Where PREDIS = 0
HI = RHC: Read to Read from same bank
HI = RHC + IC: Read to Read from different bank
HI = RHC + Max (IC, (4 × tDDR2_CLK)): Read to Write from same or different bank
Where PREDIS = 1
HI = RHC + Max (IC, (4 × tDDR2_CLK)): Read to Write from same or different bank
HI = RHC + (3 × tDDR2_CLK): Read to Read from same bank
HI = RHC + Max (IC, (3 × tDDR2_CLK)): Read to Read from different bank
IC = (number of idle cycles specified in AMICTLx register) × tDDR2_CLKH = (number of hold cycles specified in AMICTLx register) × tDDR2_CLK
1 Data delay/setup: System must meet tDAD, tDRLD, or tSDS.
2 The falling edge of AMI_MSx, is referenced.
3 The maximum limit of timing requirement values for tDAD and tDRLD parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not
used.
4 Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.
5 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 62 for the calculation of hold times given capacitive and dc loads.
6 AMI_ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low).
Rev. B | Page 35 of 76 | March 2013
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