ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
ADSP-21469/ADSP-21469W
Preliminary Technical Data
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK, (setup skew = tLCLK-
TWH min– tDLDCH – tSLDCL). Hold skew is the maximum delay
that can be introduced in LCLK relative to LDATA, (hold skew
= tLCLKTWL min – tHLDCH – tHLDCL). Calculations made directly
from speed specifications will result in unrealistically small skew
times because they include multiple tester guardbands. The
setup and hold skew times shown below are calculated to
include only one tester guardband.
ADSP-21469 Setup Skew = TBD ns max
ADSP-21469 Hold Skew = TBD ns max
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
Table 28. Link Ports – Receive
Parameter
Min
Max
Timing Requirements
tSLDCL
Data Setup Before LCLK Low
tHLDCL
Data Hold After LCLK Low
tLCLKIW
LCLK Period
tLCLKRWL
LCLK Width Low
tLCLKRWH
LCLK Width High
Switching Characteristics
tDLALC
LACK Low Delay After LCLK High1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1 LACK goes low with tDLALC relative to rise of LCLK after first byte, but does not go low if the receiver's link buffer is not about to fill.
Unit
ns
ns
ns
ns
ns
ns
LCLK
LDAT7-0
LACK (OUT)
tLCLKRWH
tLCLKIW
tLCLKRWL
tSLDCL
IN
tHLDCL
tDLALC
Figure 20. Link Ports—Receive
Rev. PrB | Page 32 of 56 | November 2008
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