ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
Preliminary Technical Data
ADSP-21469/ADSP-21469W
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 34. IDP
signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1
pins using the SRU. Therefore, the timing specifications pro-
vided below are valid at the DAI_P20–1 pins.
Table 34. Input Data Port (IDP)
Parameter
Min
Max
Unit
Timing Requirements
tSISFS1
FS Setup Before SCLK Rising Edge
tSIHFS1
FS Hold After SCLK Rising Edge
tSISD1
SData Setup Before SCLK Rising Edge
tSIHD1
SData Hold After SCLK Rising Edge
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
tIDPCLKW
tIDPCLK
Clock Width
Clock Period
TBD
TBD
ns
TBD
TBD
ns
1 AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
tIPDCLKW
SAMPLE EDGE
tIPDCLK
tSISFS
tSIHFS
tSISD
tSIHD
Figure 24. IDP Master Timing
Sample Rate Converter—Serial Input Port
The ASRC input signals (SCLK, FS, and SDATA) are routed
from the DAI_P20–1 pins using the SRU. Therefore, the timing
specifications provided in Table 35 are valid at the DAI_P20–1
pins.
Table 35. ASRC, Serial Input Port
Parameter
Min
Max
Unit
Timing Requirements
tSRCSFS1
tSRCHFS1
tSRCSD1
tSRCHD1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
tSRCCLKW
Clock Width
TBD
TBD
ns
tSRCCLK
Clock Period
TBD
TBD
ns
1 AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
Rev. PrB | Page 37 of 56 | November 2008
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