ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
Preliminary Technical Data
ADSP-21469/ADSP-21469W
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the
drive edge.
Table 36. ASRC, Serial Output Port
Parameter
Min
Max
Unit
Timing Requirements
tSRCSFS1
tSRCHFS1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
TBD
TBD
ns
TBD
TBD
ns
tSRCCLKW
Clock Width
TBD
TBD
ns
tSRCCLK
Clock Period
TBD
TBD
ns
Switching Characteristics
TBD
TBD
tSRCTDD1
tSRCTDH1
Transmit Data Delay After SCLK Falling Edge
Transmit Data Hold After SCLK Falling Edge
TBD
TBD
ns
TBD
TBD
ns
1 AMI_DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
SAMPLE EDGE
tSRCCLK
tSRCCLKW
tSRCSFS
tSRCHFS
tSRCTDD
tSRCTDH
Figure 26. ASRC Serial Output Port Timing
Rev. PrB | Page 39 of 56 | November 2008
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