ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
ADSP-21469/ADSP-21469W
Preliminary Technical Data
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 30. Serial Ports—External Clock
Parameter
Timing Requirements
tSFSE1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tHFSE1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tSDRE1
tHDRE1
Receive Data Setup Before Receive SCLK
Receive Data Hold After SCLK
tSCLKW
SCLK Width
tSCLK
SCLK Period
Switching Characteristics
tDFSE2
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
tHOFSE2
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
tDDTE2
tHDTE2
Transmit Data Delay After Transmit SCLK
Transmit Data Hold After Transmit SCLK
1 Referenced to sample edge.
2 Referenced to drive edge.
Min
Max
Unit
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
Table 31. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tHFSI1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tSDRI1
Receive Data Setup Before SCLK
tHDRI1
Receive Data Hold After SCLK
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
Switching Characteristics
TBD
TBD
tDFSI2
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
TBD
TBD
ns
tHOFSI2
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
TBD
TBD
ns
tDFSIR2
FS Delay After SCLK (Internally Generated FS in Receive Mode)
TBD
TBD
ns
tHOFSIR2
FS Hold After SCLK (Internally Generated FS in Receive Mode)
TBD
TBD
ns
tDDTI2
Transmit Data Delay After SCLK
TBD
TBD
ns
tHDTI2
Transmit Data Hold After SCLK
TBD
TBD
ns
tSCKLIW
Transmit or Receive SCLK Width
TBD
TBD
ns
1 Referenced to the sample edge.
2 Referenced to drive edge.
Rev. PrB | Page 34 of 56 | November 2008
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