ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
Preliminary Technical Data
Table 29. Link Ports – Transmit
Parameter
Timing Requirements
tSLACH
LACK Setup Before LCLK High
tHLACH
LACK Hold After LCLK High
Switching Characteristics
tDLDCH
tHLDCH
tLCLKTWL
tLCLKTWH
tDLACLK
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay After LACK High
ADSP-21469/ADSP-21469W
Min
Max
Unit
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
tLCLKTWH
tLCLKTWL
LAST BYTE
TRANSMITTED
FIRST BYTE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LCLK
tHLDCH
tDLDCH
LDAT7-0
OUT
tSLACH
tHLACH
LACK (IN)
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST BYTE TRANSMITTED.
tDLACLK
Figure 21. Link Ports—Transmit
Rev. PrB | Page 33 of 56 | November 2008
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