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ADSP-21990 View Datasheet(PDF) - Analog Devices

Part Name
Description
MFG CO.
ADSP-21990
ADI
Analog Devices ADI
'ADSP-21990' PDF : 50 Pages View PDF
ADSP-21990
External Port Bus Request/Grant Cycle Timing
Table 11 and Figure 12 describe external port bus request and
bus grant operations.
Table 11. External Port Bus Request and Grant Cycle Timing
Parameter1, 2
Min
Timing Requirements
tBS
BR Asserted to CLKOUT High Setup
4.6
tBH
CLKOUT High to BR Deasserted Hold Time
0
Switching Characteristics
tSD
CLKOUT High to xMS, Address, and RD/WR Disable
tSE
CLKOUT Low to xMS, Address, and RD/WR Enable
0
tDBG
CLKOUT High to BG Asserted Setup
0
tEBG
CLKOUT High to BG Deasserted Hold Time
0
tDBH
CLKOUT High to BGH Asserted Setup
0
tEBH
CLKOUT High to BGH Deasserted Hold Time
0
1 tHCLK is the peripheral clock period.
2 These are timing parameters that are based on worst-case operating conditions.
Max
0.5tHCLK + 1
4
4
4
4
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
tBS
BR
MS3–0
IOMS
BMS
A21–0
WR
RD
BG
BGH
tBH
tSD
tSD
tSD
tDBG
tDBH
Figure 12. External Port Bus Request and Grant Cycle Timing
tSE
tSE
tSE
tEBG
tEBH
Rev. A | Page 32 of 50 | August 2007
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