ADSP-21990 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21990' PDF : 50 Pages View PDF
Serial Peripheral Interface Port—Master Timing
Table 13 and Figure 16 describe SPI port master operations.
Table 13. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPID
tHSPID
Data Input Valid to SCLK Edge (Data Input Setup)
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
Switching Characteristics
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tDDSPID
tHDSPID
SPISEL Low to First SCLK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCLK Edge to SPISEL High
Sequential Transfer Delay
SCLK Edge to Data Output Valid (Data Out Delay)
SCLK Edge to Data Output Invalid (Data Out Hold)
ADSP-21990
Min
8
1
2tHCLK – 3
2tHCLK – 3
2tHCLK – 3
4tHCLK – 1
2tHCLK – 3
2tHCLK – 2
0
0
Max
6
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPISEL
(OUTPUT)
tSPICHM
SCLK
(CPOL = 0)
(OUTPUT)
SCLK
(CPOL = 1)
(OUTPUT)
tSDSCIM
tSPICLM
MOSI
(OUTPUT)
tSPICLM
tSPICHM
tDDSPID
MSB
CPHA = 1
MISO
(INPUT)
MOSI
(OUTPUT)
CPHA = 0
tSSPID
MISO
(INPUT)
tSSPID
MSB
VALID
tHSPID
tDDSPID
MSB
MSB
VALID
tHSPID
tSPICLK
tHDSM
tSPITDM
tHDSPID
LSB
tSSPID
LSB
VALID
tHDSPID
LSB
tHSPID
LSB
VALID
Figure 16. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. A | Page 37 of 50 | August 2007
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