ADSP-21990 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21990' PDF : 50 Pages View PDF
ADSP-21990
Serial Peripheral Interface Port—Slave Timing
Table 14 and Figure 17 describe SPI port slave operations.
Table 14. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
tSSPID
tHSPID
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SPICLK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SPICLK Edge
Data Input Valid to SCLK Edge (Data Input Setup)
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
Switching Characteristics
tDSOE
tDSDHI
tDDSPID
tHDSPID
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
SCLK Edge to Data Out Valid (Data Out Delay)
SCLK Edge to Data Out Invalid (Data Out Hold)
Min
2tHCLK
2tHCLK
4tHCLK
2tHCLK
2tHCLK + 4
2tHCLK
1.6
2.4
0
0
0
0
Max
8
10
10
10
SPISS
(INPUT)
SCLK
(CPOL = 0)
(INPUT)
SCLK
(CPOL = 1)
(INPUT)
tDSOE
MISO
(OUTPUT)
CPHA = 1
MOSI
(INPUT)
tDSOE
MISO
(OUTPUT)
CPHA = 0
MOSI
(INPUT)
tSPICHS
tSPICLS
tSPICLK
tHDS
tSPITDS
tSPICLS
tSDSCI
tSPICHS
tDDSPID tHDSPID
MSB
tSSPID
MSB
VALID
tDDSPID
tHSPID
MSB
MSB
VALID
tDDSPID
tDSDHI
LSB
tSSPID
LSB
VALID
tHSPID
tDSDHI
LSB
tSSPID
LSB
VALID
tHSPID
Figure 17. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. A | Page 38 of 50 | August 2007
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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