ADSP-21990 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21990' PDF : 50 Pages View PDF
ADSP-21990
JTAG Test And Emulation Port Timing
Table 15 and Figure 18 describe JTAG port operations.
Table 15. JTAG Port Timing
Parameter
Timing Requirements
tTCK
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1
TRST Pulse Width2
Min
Max
20
4
4
4
5
4tTCK
Switching Characteristics
tDTDO
tDSYS
TDO Delay from TCK Low
System Outputs Delay After TCK Low3
8
0
22
1 System inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF15–0, DR, TCLK, RCLK, TFS, RFS, CLKIN, RESET.
2 50 MHz maximum.
3 System outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF15–0, DT, TCLK0, TCLK, RCLK, TFS, RFS, BMS.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
tH SYS
tDSYS
Figure 18. JTAG Port Timing
Rev. A | Page 39 of 50 | August 2007
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