ADSP-BF537BBCZ-5AV View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF537BBCZ-5AV' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
External Port Bus Request and Grant Cycle Timing
Table 26 and Figure 13 describe external port bus request and
bus grant operations.
Table 26. External Port Bus Request and Grant Cycle Timing
Parameter1, 2
Timing Requirements
tBS
BR Asserted to CLKOUT Low Setup
tBH
CLKOUT Low to BR Deasserted Hold Time
Switching Characteristics
tSD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
tSE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
tDBG
CLKOUT High to BG Asserted Setup
tEBG
CLKOUT High to BG Deasserted Hold Time
tDBH
CLKOUT High to BGH Asserted Setup
tEBH
CLKOUT High to BGH Deasserted Hold Time
1 These timing parameters are based on worst-case operating conditions.
2 The pad loads for these timing parameters are 20 pF.
Min
Max
Unit
4.6
ns
0.0
ns
4.5
ns
4.5
ns
3.6
ns
3.6
ns
3.6
ns
3.6
ns
CLKOUT
BR
AMSx
ADDR 19-1
ABE1-0
AWE
ARE
BG
BGH
tBS
tBH
tSD
tSD
tSD
tDBG
tDBH
Figure 13. External Port Bus Request and Grant Cycle Timing
tSE
tSE
tSE
tEBG
tEBH
Rev. J | Page 33 of 68 | February 2014
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