ADSP-BF534/ADSP-BF536/ADSP-BF537
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
RSCLKx
SAMPLE EDGE
tHOFSI
RFSx
(OUTPUT)
tDFSI
RFSx
(INPUT)
tSFSI
tHFSI
DRx
tSDRI
tHDRI
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
tSCLKEW
tSCLKE
RSCLKx
tHOFSE
RFSx
(OUTPUT)
tDFSE
RFSx
(INPUT)
tSFSE
tHFSE
DRx
tSDRE
tHDRE
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
tSCLKIW
TSCLKx
SAMPLE EDGE
tHOFSI
TFSx
(OUTPUT)
tD FSI
TFSx
(INPUT)
DTx
tHDTI
tDDTI
tSFSI
tHFSI
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
tSCLKE
t SCLKEW
TSCLKx
tHOFSE
TFSx
(OUTPUT)
tDFSE
TFSx
(INPUT)
DTx
tHDTE
tDDTE
tSFSE
tHFSE
Figure 20. Serial Ports
TSCLKx
(INPUT)
TFSx
(INPUT)
tSUDTE
RSCLKx
(INPUT)
RFSx
(INPUT)
tSUDRE
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED
Figure 21. Serial Port Start Up with External Clock and Frame Sync
Rev. J | Page 39 of 68 | February 2014