ADSP-BF537BBCZ-5AV View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF537BBCZ-5AV' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
Parallel Peripheral Interface Timing
Table 29 and Figure 16 on Page 36, Figure 20 on Page 39, and
Figure 23 on Page 41 describe parallel peripheral interface
operations.
Table 29. Parallel Peripheral Interface Timing
Parameter
Min
Timing Requirements
tPCLKW
PPI_CLK Width1
6.0
tPCLK
PPI_CLK Period1
15.0
Timing Requirements—GP Input and Frame Capture Modes
tSFSPE
External Frame Sync Setup Before PPI_CLK
6.7
tHFSPE
External Frame Sync Hold After PPI_CLK
1.0
tSDRPE
Receive Data Setup Before PPI_CLK
3.5
tHDRPE
Receive Data Hold After PPI_CLK
1.5
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
1.7
tDDTPE
Transmit Data Delay After PPI_CLK
tHDTPE
Transmit Data Hold After PPI_CLK
1.8
1 PPI_CLK frequency cannot exceed fSCLK/2.
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_CLK
tHOFSPE
tDFSPE
tPCLKW
PPI_FS1/2
tPCLK
tSDRPE
tHDRPE
PPI_DATA
Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing
PPI_CLK
PPI_FS1/2
PPI_DATA
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
tSFSPE
tHFSPE
tPCLKW
tPCLK
tSDRPE
tHDRPE
Figure 17. PPI GP Rx Mode with External Frame Sync Timing
Max
8.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. J | Page 36 of 68 | February 2014
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