ADSP-BF537BBCZ-5AV View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF537BBCZ-5AV' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Peripheral Interface Port—Master Timing
Table 34 and Figure 24 describe SPI port master operations.
Table 34. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
2.25 V VDDEXT 2.70 V
or
0.80 V VDDINT 0.95 V1
Min
Max
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
8.7
tHSPIDM
SCK Sampling Edge to Data Input Invalid
–1.5
Switching Characteristics
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tDDSPIDM
tHDSPIDM
SPISELx Low to First SCK Edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISELx High
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
6
–1.0
1 Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
2 Applies to all nonautomotive-grade devices when operated within these voltage ranges.
3 All automotive-grade devices are within these specifications.
2.70 V VDDEXT 3.60 V
and
0.95 V VDDINT 1.43 V2, 3
Min
Max
7.5
–1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
4 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
6
–1.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
SPIxMOSI
(OUTPUT)
CPHA = 1
SPIxMISO
(INPUT)
tSDSCIM
tSPICLM
tSPICHM
tHDSPIDM
tSPICLK
tHDSM
tSPITDM
tDDSPIDM
tSSPIDM
tHSPIDM
SPIxMOSI
(OUTPUT)
CPHA = 0
tSSPIDM
SPIxMISO
(INPUT)
tHSPIDM
tHDSPIDM
tDDSPIDM
Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. J | Page 42 of 68 | February 2014
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