ADSP-BF537BBCZ-5AV View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF537BBCZ-5AV' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
JTAG Test and Emulation Port Timing
Table 39 and Figure 29 describe JTAG port operations.
Table 39. JTAG Port Timing
Parameter
Min
Max
Unit
Timing Parameters
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK High1
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulse Width2 (Measured in TCK Cycles)
Switching Characteristics
20
ns
4
ns
4
ns
4
ns
5
ns
4
TCK
tDTDO
tDSYS
TDO Delay From TCK Low
System Outputs Delay After TCK Low3
10
ns
0
12
ns
1 System Inputs = DATA15–0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH15–0, MDIO, TCK, TRST, RESET, NMI, RTXI,
BMODE2–0.
2 50 MHz maximum.
3 System Outputs = DATA15–0, ADDR19–1, ABE1–0, BG, BGH, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, MDC, MDIO,
TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTXO, TDO, EMU, XTAL, VROUT1–0.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP
tDTDO
tDSYS
tSSYS
tHTAP
tHSYS
Figure 29. JTAG Port Timing
Rev. J | Page 46 of 68 | February 2014
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