ADSP-BF537BBCZ-5AV View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF537BBCZ-5AV' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
Timer Clock Timing
Table 37 and Figure 27 describe timer clock timing.
Table 37. Timer Clock Timing
Parameter
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
Min
Max
Unit
12
ns
PPI_CLK
TMRx OUTPUT
tTODP
Figure 27. Timer Clock Timing
Timer Cycle Timing
Table 38 and Figure 28 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (fSCLK/2) MHz.
Table 38. Timer Cycle Timing
Parameter
2.25 V VDDEXT 2.70 V
or
0.80 V VDDINT 0.95 V1
Min
Max
2.70 V VDDEXT 3.60 V
and
0.95 V VDDINT 1.43 V2, 3
Min
Max
Unit
Timing Characteristics
tWL
Timer Pulse Width Input Low (Measured In SCLK Cycles)4 1 × tSCLK
1 × tSCLK
ns
tWH
Timer Pulse Width Input High (Measured In SCLK Cycles)4 1 × tSCLK
1 × tSCLK
ns
tTIS
Timer Input Setup Time Before CLKOUT Low5
5.5
5.0
ns
tTIH
Timer Input Hold Time After CLKOUT Low5
1.5
1.5
ns
Switching Characteristics
tHTO
Timer Pulse Width Output (Measured In SCLK Cycles)
1 × tSCLK
(232–1) × tSCLK 1 × tSCLK
(232–1) × tSCLK ns
tTOD
Timer Output Update Delay After CLKOUT High
6.5
6.0
ns
1 Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
2 Applies to all nonautomotive-grade devices when operated within these voltage ranges.
3 All automotive-grade devices are within these specifications.
4 The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
5 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
TMRx OUTPUT
TMRx INPUT
tTOD
tTIS
tTIH
tHTO
tWH,tWL
Figure 28. Timer Cycle Timing
Rev. J | Page 45 of 68 | February 2014
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