ATA6612C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6612C
Atmel Corporation
'ATA6612C' PDF : 312 Pages View PDF
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable
operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable
behavior. If changes of more than 2% is required, ensure that the MCU is kept in reset during the changes.
Note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still
ensuring stable operation. Refer to Section 5.6.11 “System Clock Prescaler” on page 54 for details.
5.6.9
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed.
This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during
reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the
internal RC oscillator, can be selected when the clock is output on CLKO. If the system clock prescaler is used, it is the
divided system clock that is output.
5.6.10 Timer/Counter Oscillator
The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a external clock source. The
Timer/Counter oscillator pins (TOSC1 and TOSC2) are shared with XTAL1 and XTAL2. This means that the Timer/Counter
oscillator can only be used when an internal RC oscillator is selected as system clock source. See Figure 5-12 on page 48
for crystal connection.
Applying an external clock source to TOSC1 requires EXTCLK in the ASSR register written to logic one. See Section 5.15.9
“Asynchronous Operation of the Timer/Counter” on page 153 for further description on selecting external clock as input
instead of a 32kHz crystal.
5.6.11 System Clock Prescaler
The Atmel® ATA6612C/ATA6613C has a system clock prescaler, and the system clock can be divided by setting the
Section 5.6.11.1 “Clock Prescale Register – CLKPR” on page 54. This feature can be used to decrease the system clock
frequency and the power consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and
clkFLASH are divided by a factor as shown in Table 5-20 on page 62.
When switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system.
It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous
setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at
the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to
determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to
the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and
T1 + 2 × T2
before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock
period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:
1. Write the clock prescaler change enable (CLKPCE) bit to one and all other bits in CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
5.6.11.1Clock Prescale Register – CLKPR
Bit
7
6
5
4
3
2
1
0
CLKPCE
–
–
–
CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated
when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it
is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend
the time-out period, nor clear the CLKPCE bit.
54 ATA6612C/ATA6613C [DATASHEET]
9111L–AUTO–11/14
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