ATA6612C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6612C
Atmel Corporation
'ATA6612C' PDF : 312 Pages View PDF
5.7.8 Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in an AVR® controlled system. In
general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as
possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following
modules may need special consideration when trying to achieve the lowest possible power consumption.
5.7.8.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any
sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to
Section 5.21 “Analog-to-Digital Converter” on page 224 for details on ADC operation.
5.7.8.2 Analog Comparator
When entering Idle mode, the analog comparator should be disabled if not used. When entering ADC noise reduction mode,
the analog comparator should be disabled. In other sleep modes, the analog comparator is automatically disabled. However,
if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in
all sleep modes. Otherwise, the internal voltage reference will be enabled, independent of sleep mode. Refer to
Section 5.20 “Analog Comparator” on page 221 for details on how to configure the analog comparator.
5.7.8.3 Brown-out Detector
If the brown-out detector is not needed by the application, this module should be turned off. If the brown-out detector is
enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption. Refer to
Section 5.8.5 “Brown-out Detection” on page 63 for details on how to configure the brown-out detector.
5.7.8.4 Internal Voltage Reference
The internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the ADC.
If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will
not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If
the reference is kept on in sleep mode, the output can be used immediately. Refer to Section 5.8.8 “Internal Voltage
Reference” on page 65 for details on the start-up time.
5.7.8.5 Watchdog Timer
If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it
will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute
significantly to the total current consumption. Refer to Section 5.8.9 “Watchdog Timer” on page 66 for details on how to
configure the watchdog timer.
5.7.8.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure
that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped,
the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed.
In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section
Section 5.10.2.5 “Digital Input Enable and Sleep Modes” on page 81 for details on which pins are enabled. If the input buffer
is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive
power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input
pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the digital input
disable registers (DIDR1 and DIDR0). Refer to Section 5.20.3.1 “Digital Input Disable Register 1 – DIDR1” on page 223 and
Section 5.21.6.5 “Digital Input Disable Register 0 – DIDR0” on page 238 for details.
5.7.8.7 On-chip Debug System
If the on-chip debug system is enabled by the DWEN fuse and the chip enters sleep mode, the main clock source is enabled
and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current
consumption.
ATA6612C/ATA6613C [DATASHEET]
59
9111L–AUTO–11/14
Share Link: 