ATA6612C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6612C
Atmel Corporation
'ATA6612C' PDF : 312 Pages View PDF
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits can
be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master
clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.
The division factors are given in Table 5-17.
The CKDIV8 fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be
reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This
feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device
at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
fuse setting. The application software must ensure that a sufficient division factor is chosen if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operating conditions. The
device is shipped with the CKDIV8 fuse programmed.
Table 5-17. Clock Prescaler Select
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
1
2
4
8
16
32
64
128
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5.7 Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR® provides
various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be
executed. The SM2, SM1, and SM0 bits in the SMCR register select which sleep mode (idle, ADC noise reduction,
power-down, power-save, or standby) will be activated by the SLEEP instruction. See Table 5-18 on page 56 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles
in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP.
The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during
sleep mode, the MCU wakes up and executes from the reset vector.
Figure 5-11 on page 46 presents the different clock systems in the Atmel® ATA6612C/ATA6613C, and their distribution. The
figure is helpful in selecting an appropriate sleep mode.
ATA6612C/ATA6613C [DATASHEET]
55
9111L–AUTO–11/14
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