ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
13.5.4 L2CC Auxiliary Control Register
Name:
L2CC_ACR
Address: 0x00A00104
Access: Read/Write in Secure mode
Read-only in Non-secure mode
31
30
29
–
–
IPEN
28
DPEN
27
NSIAC
26
NSLEN
25
CRPOL
24
FWA
23
FWA
22
SAOEN
21
PEN
20
EMBEN
19
18
17
WAYSIZE
16
ASS
15
14
13
12
11
10
9
8
–
–
SAIE
EXCC
SBDLE
HPSO
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
Note: The L2 Cache Controller (L2CC) must be disabled in the L2CC Control Register prior to any write access to this register.
• HPSO: High Priority for SO and Dev Reads Enable
0: Strongly Ordered and Device reads have lower priority than cacheable accesses when arbitrated in the L2CC master
ports. This is the default value.
1: Strongly Ordered and Device reads get the highest priority when arbitrated in the L2CC master ports.
• SBDLE: Store Buffer Device Limitation Enable
0: Store buffer device limitation is disabled. Device writes can take all slots in the store buffer. This is the default value.
1: Store buffer device limitation is enabled.
• EXCC: Exclusive Cache Configuration
0: Disabled. This is the default value.
1: Enabled.
• SAIE: Shared Attribute Invalidate Enable
0: Shared invalidate behavior is disabled. This is the default value.
1: Shared invalidate behavior is enabled if the Shared Attribute Override Enable bit is not set.
Shared invalidate behavior is enabled if both:
• Shareable Attribute Invalidate Enable bit is set in the Auxiliary Control Register, bit[13]
• Shared Attribute Override Enable bit is not set in the Auxiliary Control Register, bit[22]
• ASS: Associativity
0: 8-way.This is the default value.
1: Reserved.
SAMA5D4 Series [DATASHEET]
93
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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