ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
• WAYSIZE: Way Size
Value Name
0x0 RESERVED
0x1 16KB_WAY
0x2 RESERVED
0x3 RESERVED
0x4 RESERVED
0x5 RESERVED
0x6 RESERVED
0x7 RESERVED
Description
Reserved
16-Kbyte way set associative
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
• EMBEN: Event Monitor Bus Enable
0: Disabled. This is the default value.
1: Enabled.
• PEN: Parity Enable
0: Disabled. This is the default value.
1: Enabled.
• SAOEN: Shared Attribute Override Enable
0: Treats shared accesses. This is the default value.
1: Shared attribute is internally ignored.
• FWA: Force Write Allocate
0: The L2 Cache controller uses AWCACHE attributes for WA. This is the default value.
1: User forces no allocate, WA bit must be set to 0.
2: User overrides AWCACHE attributes, WA bit must be set to 1. All cacheable write misses become write allocated.
3: The write allocation is internally mapped to 00.
• CRPOL: Cache Replacement Policy
0: Pseudo-random replacement using the LFSR algorithm.
1: Round-robin replacement. This is always the default value.
• NSLEN: Non-Secure Lockdown Enable
0: Lockdown registers cannot be modified using non-secure accesses. This is the default value.
1: Non-secure accesses can write to the lockdown registers.
• NSIAC: Non-Secure Interrupt Access Control
0: Interrupt Clear Register and Interrupt Mask Register can only be modified or read with secure accesses. This is the
default value.
1: Interrupt Clear Register and Interrupt Mask Register can be modified or read with secure or non-secure accesses.
94 SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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