ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

ATSAMA5D41A-CU

SMART ARM-based Embedded MPU

Atmel Corporation 

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13.5.6 L2CC Data RAM Latency Control Register

Name:

L2CC_DRCR

Address: 0x00A0010C

Access: Read/Write in Secure mode

Read-only in Non-secure mode

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

–

–

–

–

–

15

14

13

12

11

10

9

8

–

–

–

–

–

DWRLAT

7

6

5

4

3

2

1

0

–

DRDLAT

–

DSETLAT

Note: The L2 Cache Controller (L2CC) must be disabled in the L2CC Control Register prior to any write access to this register.

• DSETLAT: Setup Latency

• DRDLAT: Read Access Latency

• DWRLAT: Write Access Latency

Latency to Data RAM is the programmed value + 1.

Default value is 0.

SAMA5D4 Series [DATASHEET]

97

Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16

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