13.5.7 L2CC Event Counter Control Register
Name:
L2CC_ECR
Address: 0x00A00200
Access: Read/Write
31
30
29
28
–
–
–
–
23
22
21
20
–
–
–
–
15
14
13
12
–
–
–
–
7
6
5
4
–
–
–
–
• EVCEN: Event Counter Enable
0: Disables Event Counter. This is the default value.
1: Enables Event Counter.
• EVC0RST: Event Counter 0 Reset
0: No effect, always read as zero.
1: Resets Counter 0.
• EVC1RST: Event Counter 1 Reset
0: No effect, always read as zero.
1: Resets Counter 1.
27
26
25
24
–
–
–
–
19
18
17
16
–
–
–
–
11
10
9
8
–
–
–
–
3
2
1
0
–
EVC1RST
EVC0RST
EVCEN
98 SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16