CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
11.7.1 Extension Control 1
Register Name: Extension Control 1
I/O Index: 2Fh Extended Index: 03h
Memory Offset: 903h
Register Per: socket
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DREQ Enable
Pull-Up
Control
Reserved
LED Activity
Enable
Reserved
VCC Power
Lock
R/W:00
R/W:0
R/W:0
R/W:0
R/W:0
R/W:0
R/W:0
Bit 0 — VCC Power Lock
0
The VCC Power bit (bit 4 of Power Control register) is not locked.
1
The VCC Power bit (bit 4 of Power Control register) cannot be changed by software.
This bit can be used to prevent card drivers from overriding the Socket Services’ task of controlling
power to the card, thus preventing situations where cards are powered incorrectly.
Bit 1 — Reserved
Bit 2 — LED Activity Enable
0
LED activity disabled.
1
LED activity enabled.
This bit allows the LED_OUT* and LED1* or LED2* pin corresponding to the socket to reflect any
activity in the card. Whenever PC Card cycles are in process to or from a card in the respective
sockets, LED1* or LED2* pin is active low.
Bits 4:3 — Reserved
Bit 5 — Pull-Up Control
0
Pull-ups on VS2, VS1, CD2, and CD1 are in use.
1
Pull-ups on VS2, VS1, CD2, and CD1 are turned off.
This bit turns off the pull-ups on VS2, VS1, CD2, and CD1. Turning off these pull-ups can be used
in addition to Suspend mode to even further reduce power when cards are inserted, but no card
accessibility is required. Even though power may or may not still be applied, all pull-ups and their
associated inputs are disabled.
Note that insertion or removal of a card cannot be determined when this bit is set to ‘1’. Also, when
a card is already in the socket, a card detect interrupt is generated when this bit is changed from
‘0’ to ‘1’.
Bits 7:6 — DREQ Enable
These bits are used to identify which PC Card 16 pin is used for DREQ, and enable the DMA
operation of the socket. At reset these bits are reset and this disables the DREQ line. When either
or both of these bits are set, the DREQ pin is selected by the following table.
Bit 7
Bit 6
Pin Used
0
0
0
1
1
0
1
1
DREQ Disabled
INPACK#
WP/IOIS16
BVD2/SPKR#
142
EXTENSION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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