CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
11.7.3 Pin Multiplex Control 0 Register — PME_CXT
Register Name: Pin Multiplex Control 0 Register — PME_CXT
I/O Index: 2Fh Extended Index: 14h
Memory Offset: 914h (for function 0 only)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Register Per: chip
Register Compatibility Type: ext.
Bit 2
Bit 1
Bit 0
LED_OUT*/HW_SUSP*/
PME#/GPIO4
SPKR_OUT*/GPIO3
SIN#/ISDAT/
LED2*/GPIO2
INTA#/LED1*/GPIO1
Select 1
R/W:0
Select 0
R/W:0
Select 1
R/W:0
Select 0
R/W:0
Select 1
R/W:0
Select 0
R/W:0
Select 1
R/W:0
Select 0
R/W:0
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 through a software PCI Bus Segment reset.
Bits 1:0 — INTA#/LED1*/GPIO1 Select 1:0
These bits select the function of pin 203.
Bit 1
Bit 0
Pin Function
0
0
INTA# or LED1*a
0
1
GPIO1
1
0
Do not program this value.
1
1
Do not program this value.
a The socket A LED indicator, active-low OD, or LED_OUT* if configured for one LED.
Bits 3:2 — SIN#/ISDAT/LED2*/GPIO2 Select 1:0
These bits select the function of pin 206.
Bit 3
Bit 2
Pin Function
0
0
SIN#, ISDAT, or LED2* with control of pin characteristics per the
CL-PD6833 bitsa
0
1
GPIO2
1
0
Do not program this value.
1
1
Do not program this value.
a The socket B LED indicator, active-low OD, or LED_OUT* if configured for one LED (dual socket is ‘0’).
LED1* and LED2* features are only available in PCI/Way interrupt signalling mode.
144
EXTENSION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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