CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
11.7.7 GPIO Output Data
Register Name: GPIO Output Data
I/O Index: 2Fh Extended Index: 1Ah
Memory Offset: 91Ah
Bit 7
Bit 6
Bit 5
Reserved
R/W:0
Register Per: chip
Register Compatibility Type: ext.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO4 Output GPIO3 Output GPIO2 Output GPIO1 Output
Data
Data
Data
Data
R/W:0
R/W:0
R/W:0
R/W:0
Bits 3:0 — GPIO[4:1] Output Data
When in the output mode, data written to this register is driven onto the corresponding GPIO pin.
This register reads back what was last written, regardless of the state of the GPIO pins.
Bits 7:4 — Reserved
11.7.8 GPIO Input Data
Register Name: GPIO Input Data
I/O Index: 2Fh Extended Index: 1Bh
Memory Offset: 91Bh
Bit 7
Bit 6
Bit 5
Reserved
R/W:0
Register Per: chip
Register Compatibility Type: ext.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO4 Input GPIO3 Input GPIO2 Input GPIO1 Input
Data
Data
Data
Data
R:1
R:1
R:1
R:1
Bits 3:0 — GPIO[4:1] Input Data
If the corresponding GPIO Output Control and GPIO Input Control bits are both low, this address
reads back a ‘1’. In any other case, this address reads the actual state of the GPIO pins whether
in input or output mode. In the output mode, the data read from a pin can be compared to the
corresponding data bit in the GPIO Output Data register to verify that there is not a problem with
that output.
Bits 7:4 — Reserved
148
EXTENSION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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